Title: A Novel Obstacle-Aware Multiple Fan-out Symmetrical Clock Tree Synthesis
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| Authors: Liu, M; Zhang, ZW; Sun, WQ; Wang, DL
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| Author Full Names: Liu, Meng; Zhang, Zhiwei; Sun, Wenqin; Wang, Donglin
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| Source: IEICE ELECTRONICS EXPRESS, 14 (20):10.1587/elex.14.20170935 OCT 25 2017
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| Language: English
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| Abstract: Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by 17.2% while using less than 24.5% capacitance resource compared with traditional symmetrical clock tree. Further, we also validated the algorithm in ASIC design.
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| ISSN: 1349-2543
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| Article Number: 20170935
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| IDS Number: FQ5ER
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| Unique ID: WOS:000418382100012
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